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Reflective Memory System (RMS) Details

PCI-RMS Operational Modes

 

To promote maximum programming flexibility, PCI Reflective Memory board offers three modes of operation.  The board’s PCI address space is divided into three regions, each supporting a different mode.  The characteristics of each mode are described in the sections that follow.

SRAM Region

 

SRAM, the first region within PCI memory space of the PCI-RMS board, is traditional Reflective Memory.  This region is eight megabytes in size.

 

Data written to this area is automatically reflected to other boards.  This area is also updated by incoming data. The SRAM region is un-cached; thus, each transfer to or from this region requires a transaction across the PCI bus.

 

Spinlock Region

 

This region is within the PCI memory space of the PCI-RMS board, and is the same size as the SRAM region.  The Spinlock region is backed by the same physical memory as the SRAM region.  Thus, an update to location 0 of the Spinlock region will also be seen in location 0 of the SRAM region.  The Spinlock region starts at an offset of 16 megabytes above SRAM.

 

The primary difference between the SRAM and Spinlock regions is that with the SRAM region, the memory on the transmitting node is updated before the data is placed on the ring.  In the Spinlock region, the transmitting node’s memory gets updated after the data passes around the entire ring.  If the transmitting node sees the updated data, it can be sure the data was already received by every other node in the ring.

 

Memory Channel (MC) Region

 

This region is backed with a system memory buffer.  Writes are directed to the appropriate PCI address of this region.  The written data is transmitted on the ring to other nodes.  When received, the data passes through the PCIRMS board and directly into the system memory buffer of the receiving node.  All reads occur from the local buffer and not the PCI address of the region.  A maximum single transfer is 16 megabytes.  Since reads do not need to cross the PCI bus to be

accessed, they are much faster than in the other two regions. Read data is also cached in this region, offering even more speed.

Mailbox Interrupts

 

To facilitate real-time communication between nodes on the PCIRMS ring, a mailbox capability is built into the PCI-RMS board.  Each node on the ring may send an interrupt to any other specified node on the ring, or a global interrupt to all nodes on the ring.

 

Included Software Components

 

The following software components are included with PCI-RMS:

eprm driver

 

The eprm driver communicates with and handles all operations requiring access to the PCI-RMS hardware.  The eprm driver is loadable module that exports a device used by the Access Library.

 

Access Library

 

The Access Library provides an application interface to the driver, acting as a bridge between the kernel-based driver and your application.  You can call various functions in the Access Library that invoke routines in the driver to perform PCI-RMS activity.

 

PCI Reflective Memory daemon

 

The PCI Reflective Memory Daemon manages the PCI Reflective Memory partitions.  The daemon serves the PCI-RMS memory partitioning configuration file and other general information.

 

Reflective Memory Health Monitor program

 

The Reflective Memory Health Monitor checks the connectivity status of systems.  It includes a daemon that executes on each node, and a GUI-based monitor that shows the current state of each node.

 

Performance Monitor

 

The Performance Monitor allows you to test and monitor the performance of each node.  The system’s Utilities are used to monitor and control the PCIRMS environment.

To download the PCI-RMS Software product brochure, click here.

Computer Services, Inc.